When a dual damascene process is used to make an interconnect structure for a semiconductor device, a via and a trench are formed within a dielectric layer. The via and trench are then filled with copper or another conductive material. In such a process, a dual hard mask, which includes lower and upper layers, may be formed on the dielectric layer prior to forming the via and trench. When such a dual hard mask defines the trench before the via, a relatively large part of the hard mask's upper layer is removed while the lower layer serves as an etch stop. A relatively small portion of the lower layer is then removed, and a via is partially etched through the underlying dielectric layer. After an adjoining portion of the lower layer is removed, the dielectric layer may be further etched to form within it the via and trench.
Such a process, which defines the trench before the via, leaves little room for error when lining up the via. Unless the via is lined up with part of the trench, an inoperable device will result. For that reason, it is desirable for a dual damascene process, which uses such a dual hard mask, to define the via before the trench. An example of such a process, which partially etches through a first portion of the dual hard mask's lower layer to define the via prior to defining the trench, is described in Ser. No. 09/746,035, filed Dec. 22, 2000, and assigned to this application's assignee. This particular process, however, may be relatively fragile and difficult to implement.
Accordingly, there is a need for a more robust dual damascene process, which uses a dual layer hard mask, that enables the via to be defined before the trench is defined. The method of the present invention provides such a process.